In various circuit applications, heat dissipation plays an increasingly important role. With the high gate count and high operating frequency of modern system-on-a-chip (SoC) implementations, the thermal issue is escalated in prominence, especially for 2.5D or 3D integrated circuit (IC) applications. Some areas on a chip may be relatively hot and others may be relatively cool, and monitoring of the “hot spots” may be needed for effective circuit performance.
Conventional thermal sensing systems have employed devices such as transistors that exhibit temperature dependencies. In systems that use a single transistor to sense the temperature at a given location, a problem arises due to the resistance associated with routing the transistor to an adjacent (local) digital ground of a digital circuit. A voltage drop ΔV associated with such a routing resistance may degrade performance and provide an incorrect temperature reading as the value of the ΔV for each of the plurality of locations may vary. In order to overcome that ΔV problem, circuits designers have previously been forced to route the transistor to an analog ground that may be located far from the transistor to provide a common reference voltage, thereby disadvantageously increasing routing length, die area, and overall cost.
Some prior thermal sensing approaches have used a differential approach in which a pair of transistors is used to monitor temperature at a given location. The use of paired transistors addresses the foregoing ΔV problem but introduces other drawbacks. For example, using a differential transistor configuration may double the number of transistors, thereby increasing component cost and die area, which is problematic given the large number of transistors that may be used in a typical SoC thermal sensing application. Furthermore, using two devices instead of one to sense temperature introduces problems due to device mismatch (e.g., due to process variation), which may degrade performance.